?2007 fairchild semiconductor corporation 1 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) may 2007 may 2007 FSB50250S smart power module (spm ? ) features ? 500v 1.0a 3-phase frfet inverter including high voltage integrated circuit (hvic) ? 3 divided negative dc-link terminals for inverter current sens - ing applications ? hvic for gate driving and undervoltage protection ? 3/5v cmos/ttl compatible, active-high interface ? optimized for low electromagnetic interference ? isolation voltage rating of 1500vrms for 1min. ? surface mounted device package ? moisture sensitive level(msl) 3 general description FSB50250S is a tiny smart power module (spm ? ) based on frfet technology as a compact inverter solution for small power motor drive applications such as fan motors and water suppliers. it is composed of 6 fast-recovery mosfet (frfet), and 3 half-bridge hvics for frfet gate driving. FSB50250S provides low electromagnetic in terference (emi) characteristics with optimized switching speed . moreover, since it employs frfet as a power switch, it has much better ruggedness and larger safe operation area (soa) than that of an igbt-based power module or one-chip solution. the package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. f sb50250s is the most solution for the compact inverter providing the energy efficiency, compactness, and low electromagnetic interference. absolute maximum ratings symbol parameter conditions rating units v pn dc link input voltage, drain-source voltage of each frfet 500 v i d25 each frfet drain current, continuous t c = 25c 1.0 a i d80 each frfet drain current, continuous t c = 80c 0.7 a i dp each frfet drain current, peak t c = 25c, pw < 100 s 2.0 a p d maximum power dissipation t c = 25c, for each frfet 10 w v cc control supply voltage applied between v cc and com 20 v v bs high-side bias voltage applied between v b and v s 20 v v in input signal voltage applied between in and com -0.3 ~ vcc+0.3 v t j operating junction temperature -20 ~ 150 c t stg storage temperature -50 ~ 150 c r jc junction to case thermal resistance each frfet under inverter operat - ing condition (note 1) 9.3 c/w v iso isolation voltage 60hz, sinusoidal, 1 minute, con - nection pins to heatsink 1500 v rms
2 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) pin descriptions note: source terminal of each low-side mosfet is not connected to supply ground or bias voltage ground inside spm ? . external connections should be made as indicated in fig - ure 2 and 5. figure 1. pin configuration and in ternal block diag ram (bottom view) pin number pin name pin description 1 com ic common supply ground 2 v b(u) bias voltage for u phase high side frfet driving 3 v cc(u) bias voltage for u phase ic and low side frfet driving 4 in (uh) signal input for u phase high-side 5 in (ul) signal input for u phase low-side 6 v s(u) bias voltage ground for u phase high side frfet driving 7 v b(v) bias voltage for v phase high side frfet driving 8 v cc(v) bias voltage for v phase ic and low side frfet driving 9 in (vh) signal input for v phase high-side 10 in (vl) signal input for v phase low-side 11 v s(v) bias voltage ground for v phase high side frfet driving 12 v b(w) bias voltage for w phase high side frfet driving 13 v cc(w) bias voltage for w phase ic and low side frfet driving 14 in (wh) signal input for w phase high-side 15 in (wl) signal input for w phase low-side 16 v s(w) bias voltage ground for w phase high side frfet driving 17 p positive dc?link input 18 u output for u phase 19 n u negative dc?link input for u phase 20 n v negative dc?link input for v phase 21 v output for v phase 22 n w negative dc?link input for w phase 23 w output for w phase com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo (1) com (2) v b(u) (3) v cc(u) (4) in (uh) (5) in (ul) (6) v s(u) (7) v b(v) (8) v cc(v) (9) in (vh) (10) in (vl) (11) v s(v) (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) v s(w) (17) p (18) u (19) n u (20) n v (21) v (22) n w (23) w
3 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) electrical characteristics (t j = 25c, v cc =v bs =15v unless otherwise specified) inverter part (each frfet unless otherwise specified) control part (each hvic unless otherwise specified) note: 1. for the measurement point of case temperature t c , please refer to figure 3 in page 4. 2. bv dss is the absolute maximum voltage rating between drain and source terminal of each frfet inside spm ? . v pn should be sufficiently less than this value considering the effect of the stray inductance so that v ds should not exceed bv dss in any case. 3. t on and t off include the propagation delay time of the internal drive ic. listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. please see figure 4 for the switching time definition with the switching test circuit of figure 5. 4. the peak current and voltage of each frfet during the switching operation should be included in the safe operating area (soa) . please see figure 5 for the rbsoa test cir - cuit that is same as the switching test circuit. package marking & ordering information symbol parameter conditions min typ max units bv dss drain-source breakdown voltage v in = 0v, i d = 250 a (note 2) 500 - - v bv dss / t j breakdown voltage tem - perature coefficient i d = 250 a, referenced to 25c - 0.53 - v i dss zero gate voltage drain current v in = 0v, v ds = 500v - - 250 a r ds(on) static drain-source on-resistance v cc = v bs = 15v, v in = 5v, i d = 0.5a - 3.3 4.0 v sd drain-source diode forward voltage v cc = v bs = 15v, v in = 0v, i d = -0.5a - - 1.2 v t on switching times v pn = 300v, v cc = v bs = 15v, i d = 0.5a v in = 0v ? 5v, r eh = 0 inductive load l=3mh high- and low-side frfet switching (note 3) - 1273 - ns t off - 800 - ns t rr - 213 - ns e on - 42 - j e off - 2.8 - j rbsoa reverse-bias safe oper - ating area v pn = 400v, v cc = v bs = 15v, i d = i dp , v ds =bv dss , t j = 150c high- and low-side frfet switching (note 4) full square symbol parameter conditions min typ max units i qcc quiescent v cc current v cc =15v, v in =0v applied between v cc and com - - 160 a i qbs quiescent v bs current v bs =15v, v in =0v applied between v b(u) -u, v b(v) -v, v b(w) -w - - 100 a uv ccd low-side undervoltage protection (figure 6) v cc undervoltage protection detection level 7.4 8.0 9.4 v uv ccr v cc undervoltage protection reset level 8.0 8.9 9.8 v uv bsd high-side undervoltage protection (figure 7) v bs undervoltage protection detection level 7.4 8.0 9.4 v uv bsr v bs undervoltage protection reset level 8.0 8.9 9.8 v v ih on threshold voltage logic high level applied between in and com 3.0 - - v v il off threshold voltage logic low level - - 0.8 v i ih input bias current v in = 5v applied between in and com - 10 20 a i il v in = 0v - - 2 a device marking device package reel size packing type quantity FSB50250S FSB50250S spm23ba 330mm tape & reel 450
4 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) recommended oper ating conditions note: (1) it is recommended the bootstrap diode d 1 to have soft and fast recovery characteristics with 600-v rating (2) parameters for bootsrap circuit elements are dependent on pwm algorithm. for 15 khz of switching frequency, typical example of parameters is shown above. (3) rc coupling(r 5 and c 5 ) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. signal input of spm ? is compatible with standard cmos or lsttl outptus. (4) bold lines should be short and thick in pcb pattern to have small stray inductance of circuit, which results in the reductio n of surge voltage. bypass capacitors such as c 1 , c 2 and c 3 should have good high-frequency characteristics to absorb high-frequency ripple current. figure 2. recommended cpu interface and bootstrap circuit with parameters note: attach the thermocouple on top of the heatsink-side of spm ? (between spm ? and heatsink if applied) to get the correct temperature measurement. figure 3. case temperature measurement symbol parameter conditions value units min. typ. max. v pn supply voltage applied between p and n - 300 400 v v cc control supply voltage applied between v cc and com 13.5 15 16.5 v v bs high-side bias voltage applied between v b and v s 13.5 15 16.5 v v in(on) input on threshold voltage applied between in and com 3.0 - v cc v v in(off) input off threshold voltage 0 - 0.6 v t dead blanking time for preventing arm-short v cc =v bs =13.5 ~ 16.5v, t j 150c 1.0 - - s f pwm pwm switching frequency t j 150c - 15 - khz t c case temperature t j 150c -20 - 125 c com vcc lin hin vb ho vs lo p n r 3 inverter output c 3 r 1 d 1 c 1 r 2 micom 15-v line 10 f one-leg diagram of spm these values depend on pwm control algorithm * example of bootstrap paramters: c 1 = c 2 = 1 f ceramic capacitor, r 1 = 56 , r 2 = 20 r 5 c 5 hin lin v dc 0 0 0 1 1 0 1 1 open open output z 0 v dc forbidden z note both frfet off low-side frfet on high-side frfet on shoot-through same as (0, 0) c 2 case temperature(tc) detecting point 14.50mm 3.80mm mosfet case temperature(tc) detecting point 14.50mm 3.80mm mosfet
5 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) figure 4. switching time definition figure 5. switching and rbsoa(si ngle-pulse) test circuit (low-side) figure 6. undervoltage protection (low-side) figure 7. undervoltage protection (high-side) t on t rr i rr 100% of i d 120% of i d (a) turn-on t off (b) turn-off i d v ds v ds i d v in v in 10% of i d com vcc lin hin vb ho vs lo one-leg diagram of spm i d v cc r bs r eh c bs lv dc + v ds - uv ccd uv ccr input signal uv protection status low-side supply, v cc mosfet current reset detection reset uv bsd uv bsr input signal uv protection status high-side supply, v bs mosfet current reset detection reset
6 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) figure 8. example of application circuit com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo com vcc lin hin vb ho vs lo (1) com (2) v b(u) (3) v cc(u) (4) in (uh) (5) in (ul) (6) v s(u) (7) v b(v) (8) v cc(v) (9) in (vh) (10) in (vl) (11) v s(v) (12) v b(w) (13) v cc(w) (14) in (wh) (15) in (wl) (16) v s(w) (17) p (18) u (19) n u (20) n v (21) v (22) n w (23) w micom c 1 r 1 r 2 15-v supply m c 3 v dc r 1 r 1 c 1 c 1 c 2 c 2 c 2 r 3 r 4 c 4 r 5 c 5 for 3-phase current sensing and protection
7 www.fairchildsemi.com FSB50250S rev. b FSB50250S smart po wer module (spm?) detailed package outline drawings 12.00 0.20 29.00 0.20 0.60 0.10 max 1.00 (1.80) (1.30) (2.275) 4x3.90=15.60 0.30 1.95 #1 #16 #17 #23 2x3.90=7.80 0.30 0.508 0.15 0.05 5 3 1.50 0.20 (2.50) (1.30) gage plane max 3.50 12.23 0.30 13.13 0.30 13.34 0.30 seating plane (1.80) 3.10 0.20 (1.00) 17.00 0.20 0 . 5 0 + 0 . 1 0 - 0 . 0 5 #1 #16 17.90 12.30 2.80 15*1.778=26.67 1.30 13.34 0.30 15.60 7.80 4.43 2.48 land pattern recommendations 0.60 0.10 max 1.00 (1.165) 15*1.778=26.67 0.30
? 2007 fairchild semiconductor corporation www.fairchildsemi.com trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intend ed to be an exhaustive list of all such trademarks. acex ? across the board. around the world. ? activearray ? bottomless ? build it now ? coolfet ? coreplus ? crossvolt ? ctl? current transfer logic? dome ? e 2 cmos ? ecospark ? ensigna ? fact quiet series? fact ? fast ? fastr ? fps ? frfet ? globaloptoisolator ? gto ? hisec ? i-lo ? implieddisconnect ? intellimax ? isoplanar ? microcoupler ? micropak ? microwire ? motion-spm? msx ? msxpro ? ocx ? ocxpro ? optologic ? optoplanar ? pacman ? pdp-spm? pop ? power220 ? power247 ? poweredge ? powersaver ? power-spm ? powertrench ? programmable active droop ? qfet ? qs ? qt optoelectronics ? quiet series ? rapidconfigure ? rapidconnect ? scalarpump ? smart start ? spm ? stealth? superfet ? supersot ? -3 supersot ? -6 supersot ? -8 syncfet? tcm ? the power franchise ? ? tinyboost ? tinybuck ? tinylogic ? tinyopto ? tinypower ? tinywire ? trutranslation ? serdes ? uhc ? unifet ? vcx ? wire ? disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fa irchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specif ications do not expand the terms of fairchild?s worldwide terms and conditions, specifically th e warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this dat asheet contains the design specifications for product development. specifications may c hange in any manner without notice. preliminary first production this datasheet contains preliminar y data; supplementary data will be published at a later date. fairchild se miconductor reserves the right to make changes at any time wit hout notice to improve design. no identification needed full production this datasheet cont ains final specifications . fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet cont ains specifications on a product that has been discontinued by fairchild semiconducto r. the datasheet is printed for reference information only. rev. i27
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